Most tools in a semiconductor fab cost a few million dollars. ASML’s new High-NA EUV machine costs roughly $400 million per unit, needs 250 shipping crates to deliver, and takes 6 months and 250 engineers just to assemble on-site. And chipmakers are lining up to buy it.
That tells you something important about where semiconductor manufacturing is heading. The AI chip race has created a near-insatiable demand for smaller, denser transistors. High-NA EUV lithography is how the industry plans to keep delivering them. Without it, the semiconductor chips inside future AI servers, smartphones, and cloud infrastructure hit a wall. With it, the roadmap extends another decade.
Here is what this machine actually is, why it matters, and who is betting on it.
Key Takeaways
- ASML’s High-NA EUV machine, the Twinscan EXE:5200B, costs approximately $380–$400 million per unit.
- It raises numerical aperture from 0.33 to 0.55, cutting minimum feature resolution from 13nm to 8nm in a single exposure.
- The EXE:5200B delivers 2.9X higher transistor density compared to current Low-NA EUV tools.
- Intel installed the first production-grade unit in December 2025 for its 14A node.
- Samsung is acquiring two machines for 2nm and beyond; TSMC is skipping it for its A14 node and targeting A14P instead.
- Mass production using High-NA EUV is expected to begin in 2027–28.
- ASML controls 75–80% of the global EUV lithography market and is the sole supplier of High-NA EUV systems.
What Is ASML’s High-NA EUV Machine?
High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography is ASML’s next-generation chip printing system. It uses 13.5nm EUV light to expose circuit patterns onto silicon wafers, but with a significantly larger lens aperture than conventional EUV machines.
The key upgrade is the numerical aperture, which jumps from 0.33 in current Low-NA EUV tools to 0.55 in High-NA systems. That single change allows the machine to resolve features as small as 8nm in a single exposure, compared to 13nm with standard EUV. The result is roughly 2.9X higher transistor density per exposure.
There are currently two High-NA EUV models:
- EXE:5000 (R&D platform): First delivered to Intel in December 2023.
- EXE:5200B (production-capable): Intel installed the first commercial unit in December 2025 for its 14A process.
Why ASML Dominates Advanced Lithography
ASML’s position in advanced semiconductor manufacturing is unlike almost any other company in tech. It holds 100% of the global EUV lithography market, and for High-NA EUV, it has zero competition. Nobody else builds these machines.
That near-monopoly didn’t happen by accident. ASML spent over 30 years developing EUV technology, starting when the entire concept was considered too scientifically difficult to commercialize. It took billions in R&D investment, partnerships with university research labs, and deep integration with hundreds of specialized suppliers across Europe and the US.
Why Are ASML EUV Machines So Difficult to Build?
The EUV lithography process is almost absurdly complex. Here is what has to work simultaneously:
- A tin droplet is hit by a CO2 laser at 50,000 times per second, generating EUV plasma.
- That light is then bounced off a series of ultra-polished mirrors with surface accuracy measured in fractions of a nanometer.
- The entire optical system operates in a near-perfect vacuum.
- The overlay precision, meaning how accurately patterns align layer to layer, sits at 0.7nm for the EXE:5200B.
The mirrors alone require years of development and can only be manufactured by a handful of companies globally. ASML sources components from roughly 5,000 suppliers. If any single link breaks, production stalls.
Why chipmakers depend on ASML
Intel, TSMC, and Samsung don’t have an alternative. ASML EUV machines are the only tools capable of printing at the feature sizes required for advanced nodes. As of 2025, ASML’s installed base management business alone hit €8.2 billion in revenue, up 26% YoY. That revenue stream comes entirely from servicing and upgrading the fleet of EUV machines already in fabs worldwide.
What Makes High-NA EUV Different From Traditional EUV Lithography
This is the technical part. Current EUV machines use a 0.33 NA lens, which limits the smallest printable feature to about 13nm per exposure. But for smaller features, chipmakers use multi-patterning by running the same wafer through multiple exposures to build up fine structures.
High-NA EUV changes that equation.
What “High Numerical Aperture” actually means
Think of numerical aperture like the zoom on a camera lens. A higher aperture doesn’t just let in more light. It resolves finer detail. With NA 0.55, the High-NA EUV machine can focus EUV light with enough precision to print 8nm features in a single pass.
Just imagine trying to write tiny texts with a regular marker vs. a fine-point pen. High-NA is the fine-point pen. The ink (EUV light) is the same; the precision tool changes what is possible.
Why existing EUV lithography is reaching its limits
Current Low-NA EUV tools can support chip manufacturing down to the 2nm node, but beyond that, multi-patterning becomes increasingly difficult to manage at scale. ASML’s own roadmap, as laid out by former CTO Martin van den Brink, puts the limit of 0.33 NA EUV at the 1.4nm generation. Below that, without High-NA EUV, semiconductor manufacturing would be stuck.
High-NA EUV vs. Traditional EUV Lithography
| Feature | Low-NA EUV (0.33 NA) | High-NA EUV (0.55 NA) |
| Minimum resolution | 13nm | 8nm |
| Transistor density gain | Baseline | ~2.9x higher per exposure |
| Multi-patterning needed? | Yes, for sub-2nm | No, single-pass for most layers |
| Machine cost | ~$150–200M | ~$380–400M |
| Production throughput | Higher (mature tech) | 175 wafers/hour (EXE:5200B) |
| Target process nodes | 5nm to 2nm | Sub-2nm, 1.4nm and below |
| Current adoption stage | Widespread | Early production (2025–26) |
How High-NA EUV Transforms Advanced Semiconductor Chips
More transistors per millimeter of silicon means several things in practice:
- Better performance per watt: Tighter packing reduces the distance electrons travel, cutting energy use.
- More compute in the same die area: AI chip designs can pack more processing cores or memory bandwidth into the same physical space.
- Higher yields on complex chips: Fewer multi-patterning steps mean fewer chances for alignment errors that kill a wafer.
For AI chips specifically, this matters a lot. Dense transistor packing is what allows next-generation GPUs and AI accelerators to hit the compute-to-power ratios that data center operators actually need.
Inside ASML’s $400 Million High-NA EUV Machine
The EXE:5200B:
- Weighs 150,000 kg, roughly the weight of 20 double-decker buses.
- Requires 250 shipping crates to transport.
- It takes approximately 250 engineers approximately six months to install.
- Operates with 0.7nm overlay precision.
- Delivers 175 wafers per hour at a dose of 50 mJ/cm².
How large are ASML’s High-NA EUV machines?
A typical High-NA EUV system occupies a footprint larger than a tennis court. The machine isn’t a single unit but a collection of subsystems, optical columns, vacuum chambers, and laser sources that are bolted together on-site. The building has to be purpose-built or heavily modified to accommodate the floor load, vibration damping, and ultra-clean air requirements.
Why extreme precision matters in EUV Lithography
At 8nm feature resolution, a misalignment smaller than the width of a DNA strand is enough to ruin a layer. The lithographic machines compensate for vibration from surrounding equipment, thermal expansion of components, and even minor atmospheric pressure variations.
The mirrors inside the optical column are polished to atomic-level smoothness. If the largest mirror had the surface variation of a typical tabletop, it would be the size of Germany. That is what 0.7nm overlay precision actually requires.
Which Companies Are Investing in High-NA EUV?
The adoption picture right now is more fragmented than the hype suggests. Here’s the honest breakdown.
Why Intel is betting aggressively on High-NA EUV
Intel was the first company in the world to receive the EXE:5000 prototype (December 2023) and the first to install a production-grade EXE:5200B in December 2025. It has since expanded its order to two units.
Intel’s 14A process, which targets risk production in 2027 and high-volume manufacturing in 2028, is built around High-NA EUV.
How TSMC and Samsung could use High-NA EUV
The picture is more cautious here. TSMC has decided to skip High-NA EUV for its A14 node and has decided to continue optimizing its existing Low-NA EUV systems instead. The company’s target for High-NA adoption is A14P, with A14 entering mass production around 2028.
Samsung is moving faster. It’s reportedly investing KRW 1.1 trillion in High-NA EUV tools, acquiring two EXE:5200B units. The plan is to use them for 2nm foundry production, including chips like the Exynos 2600 and Tesla’s next-generation AI hardware.
SK Hynix is also in the picture, confirming an order for a production-grade High-NA EUV system in September 2025 for advanced DRAM manufacturing.
The Role of High-NA EUV in AI and Future Chip Manufacturing
Every major AI chip trend points back to the same fundamental constraint: transistor density. More transistors per chip means more compute per watt. This is the metric that determines what kind of AI model you can run, how fast, and at what energy cost.
High-NA EUV lithography is what gets the industry past the physical ceiling of current semiconductor manufacturing. Concretely:
- AI accelerators (GPUs, TPUs, NPUs) benefit from denser logic for more parallel compute.
- HBM memory stacks for AI servers need advanced DRAM nodes, which SK hynix is already targeting with High-NA EUV.
- Edge AI chips in smartphones require dense, low-power designs that only sub-2nm nodes can deliver.
- Cloud data centers are buying chips as fast as fabs can produce them; any improvement in yield or chip density directly reduces cost per inference.
The Biggest Challenges Facing ASML and High-NA EUV Adoption
I want to push back on the pure hype here. High-NA EUV is a remarkable technology, but the adoption path has real friction.
Why only a few companies can afford High-NA EUV
At $380–400 million per machine, installing the infrastructure, training engineers, and managing a six-month installation cycle, the total cost of deploying a single High-NA EUV system runs well above $1 billion when you account for all-in fab costs.
That number effectively narrows down the buyer base to TSMC, Samsung, Intel, and perhaps SK Hynix. No tier-2 company can afford a single unit. And this also means advanced semiconductor manufacturing capability in fewer hands, not more.
Could geopolitics affect ASML’s future?
ASML is a Dutch company, and it already operates under significant export restrictions. The US government has pushed the Netherlands to limit ASML’s ability to ship even standard EUV machines to China.
This creates a structural bifurcation in semiconductor manufacturing. A small cluster of Western and allied fabs has access to High-NA EUV lithography, and everyone else is limited to older DUV and Low-NA EUV technology. The geopolitical implications of that split will play out over the next decade.
ASML High-NA EUV Specifications and Industry Impact
| Specification | EXE:5200B (High-NA) |
| Numerical aperture | 0.55 |
| EUV wavelength | 13.5nm |
| Minimum resolution | 8nm (single exposure) |
| Throughput | 175 wafers/hour |
| Overlay precision | 0.7nm |
| Machine weight | 150,000 kg |
| Shipping crates required | 250 |
| Install time | ~6 months |
| Engineers are required for installation | ~250 |
| Approximate cost | ~$380–400 million |
| Target process nodes | 1.4nm, sub-2nm |
Sources: Tom’s Hardware, TrendForce
Could High-NA EUV Extend Moore’s Law?
This is the question the industry debates most seriously. Moore’s Law, the observation that transistor density doubles roughly every 2 years, has been slowing. Getting from 3nm to 2nm took longer than earlier node transitions. Getting from 2nm to 1.4nm will be harder.
High-NA EUV does extend the roadmap, at least to the 1.4nm generation. Whether it can support anything below that is an open question. ASML is already researching Hyper-NA EUV with apertures above 0.55. IBM and Lam Research are collaborating on dry resist materials that could work with High-NA EUV to push scaling past 1nm in the lab.
Optimists say the tools are there and the physics have not run out. Skeptics note that each new node requires not just better lithography but also new transistor architectures, which are independent challenges.
Why ASML May Be the Most Important Company in Semiconductor Manufacturing
There is one company in the world that builds High-NA EUV machines. There is one company in the world that even builds standard EUV machines. That company is ASML, and both Intel’s ability to reclaim process leadership and Samsung’s ability to challenge TSMC run through a single Dutch firm.
I find this position almost without parallel in modern technology. ASML doesn’t sell consumer products. Most people have never heard of it. But every AI chip in every data center, every high-end smartphone processor, every next-generation memory chip requires lithography equipment that ASML makes exclusively.
ASML controls 75–80% of the global EUV lithography market and expects a 15% year-over-year rise in total sales alongside 30% EUV business growth in 2025. High-NA EUV sales were expected to triple in 2025. None of that growth is driven by marketing. It’s driven by the fact that there is no alternative supplier.
What ASML’s High-NA EUV Means for the Future of Computing
The chips that will run LLMs five years from now, power the next wave of autonomous systems, and sit inside devices that don’t exist yet will almost certainly be manufactured using High-NA EUV lithography.
Mass production starts in 2027–28. From that point, the gap between fabs with High-NA EUV access and those without will grow, not the other way around. The companies that get there first, Intel, Samsung, and eventually TSMC, will define what semiconductor chips are capable of in the next decade.
Should the Semiconductor Industry Be Excited About High-NA EUV?
Yes, but carefully.
The technology is real, the specs are verified, and production deployments have already started. But the path from R&D to mass production is the hardest part, and it’s still ahead. TSMC’s decision to skip High-NA EUV for its A14 node is a calculated judgment that the current tools are not yet competitive in throughput and cost at scale.
What is clear: High-NA EUV lithography isn’t optional for the semiconductor industry’s long-term roadmap. It is the next mandatory step. The debate is not if, it is when, and who gets there first.
Final Thoughts
ASML’s High-NA EUV machine is the most expensive and arguably the most consequential manufacturing tool the semiconductor industry has ever built. At a price of $400 million per unit, it sits at the intersection of extreme physics, global supply chains, and trillion-dollar chip ambitions.
The near-monopoly ASML holds in EUV lithography, and especially in High-NA EUV, makes it the single most critical enabler of advanced semiconductor manufacturing today. Every roadmap for sub-2nm chips runs through Veldhoven.
The rollout over 2027–28 will tell us a lot about whether the next decade of semiconductor chips follows an aggressive or a conservative trajectory. Either way, the machine that decides it weighs 150,000 kg and takes 6 months to install.
FAQ
ASML’s High-NA EUV is a next-generation chip lithography system with a 0.55 numerical aperture, capable of printing 8nm features in a single exposure to manufacture advanced semiconductor chips.
The production-grade EXE:5200B costs approximately $380–400 million per unit, making it the most expensive manufacturing tool in the semiconductor industry.
Intel installed the first production unit in December 2025. Samsung is acquiring 2 units for 2nm production. SK Hynix has ordered one for advanced DRAM. TSMC plans to adopt it for its A14P node after 2028.
It enables 2.9X higher transistor density per exposure, allowing AI chips to pack more compute into the same die area with better energy efficiency.
Mass production using High-NA EUV machines is expected to begin in 2027–28, according to ASML CEO Christophe Fouquet, with Intel’s 14A and Samsung’s 2nm processes as early adopters.
